March 12, 2025 ~ Multi-reticle packages – optical devices with multiple reticle patterns that are user-switchable as needed – are becoming increasingly common as hyper-scale computing and other applications such as artificial intelligence (AI) adopt 2.5D to 3.5D device packaging. The advanced packaging industry, in turn, is implementing larger, panel-level packaging (PLP) to improve yield and increase throughput for […] Read More
Blogs and Articles
January 13, 2025 ~ The 3D packaging sector has been growing rapidly, driven by the expansion of chiplet packaging across the ecosystem. Chip and package sizes have also grown rapidly as 2 x 800mm2 chips are being placed in a single package along with high-bandwidth memory (HBM). Demand for these large chiplets has generated supply constraints due to how […] Read More
November 26, 2024 ~ It’s not news that artificial intelligence (AI) is driving larger and larger chip packages. For example, Nvidia’s Blackwell architecture is what is called a two-reticle package1, meaning that the chips each have an area of approximately 800mm2. Building chips and packages of this size poses myriad challenges – one of which is how many 800mm2 […] Read More
October 15, 2024 ~ Throughout this blog series, we’ve taken you on a journey through the various steps involved in developing and optimizing through-silicon vias (TSVs), which have become vital to packaging of many types of devices that require smaller-footprint, higher-density package stacks. Part 1 discussed TSV formation and the benefits of our SAPS™ megasonics for TSV cleaning; Part […] Read More
August 29, 2024 ~ ACM Research provides an advanced solution for dealing with TSV Gaps using Plasma Enhanced Chemical Vapor Deposition (PECVD) Welcome to part three of our blog series on optimizing through-silicon vias (TSVs), vertical interconnect structures vital to heterogeneous integration of multiple components for 2.5D/3D packaging techniques. Part one provided an introduction to the TSV formation process […] Read More
July 30, 2024 ~ Environmental responsibility isn’t just a tagline at ACM Research, it’s a core principle woven into the fabric of our company. We take pride in developing innovative solutions for the semiconductor industry, but we also recognize the importance of protecting the planet for future generations. During Earth Month, our Oregon team proudly collaborated with SOLVE Oregon, […] Read More
June 11, 2024 ~ Part one of this blog series on optimizing wafer-level through-silicon vias (TSV) for heterogeneous integration of multiple components and 2.5D/3D packaging provided an overview of the TSV formation process and elucidated post via cleaning solution. The SAPS™ megasonic technology developed by ACM Research enables chipmakers to remove residue following TSV formation much more effectively and completely […] Read More
May 15, 2024 ~ While heterogeneous integration of multiple components and 2.5D/3D packaging techniques pair perfectly with complex stacking architectures, these technologies elicit high demands on device manufacturing processes. Through-silicon via is the key enabler, allowing direct chip-to-chip connection through the chip stack without requiring wire bonding or edge wiring. The growing demand for miniaturized semiconductor chips and their […] Read More
February 15, 2024 ~ We enter 2024 following one of the most eventful years yet for ACM Research. This recap of our key milestones from 2023 helps illustrate why we are looking to the year ahead with great enthusiasm, as well as why we are positioned to play a leading role in the chip sector as it heads toward […] Read More
November 9, 2023 ~ The 11,000-square-foot multi-use property features offices, warehouse space and a cleanroom/demonstration lab HILLSBORO, Ore. – November 9, 2023: ACM Research, Inc. (ACM) (NASDAQ: ACMR), a leading supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging (WLP) applications, today announced the grand opening of its new multi-use facility in Hillsboro, Ore., on November 28. […] Read More